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ISL5416
TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES
ADD(2:0)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
PINS
WR
WR
WR
WR
WR
WR
WR
WR
RD
RD
RD
RD
RD
RD
RD
RD
REGISTER DESCRIPTION
Indirect Write Data Bus (15:0), “Master (15:0)”.
Indirect Write Data Bus (31:16), “Master (31:16)”.
Indirect Write Address Register for Internal Target Register (Generates a write strobe to transfer contents of the
Write Holding Register into the Target Register specified by the Indirect Address, see also Tables of Indirect
Address Registers).
Indirect Read Address Register (Used to select the Read source of data - uses the same register as Direct
Address 2 but does not generate a write strobe).
RESERVED
RESERVED
RESERVED
RESERVED
Indirect Read, Bits 15:0.
Indirect Read, Bits 31:16.
Status (15:0).
RESERVED
Channel 0 Sequenced Read Address.
Channel 1 Sequenced Read Address.
Channel 2 Sequenced Read Address.
Channel 3 Sequenced Read Address.
Power-up Sequencing
The ISL5416 core and I/O blocks are isolated by structures
which may become forward biased if the supply voltages are
not at specified levels. During the power-up and power-down
operations, differences in the starting point and ramp rates of
the two supplies may cause current to flow in the isolation
structures which, when prolonged and excessive, can
reduce the usable life of the device.
In general, the most preferred case would be to power-up
the core and I/O structures simultaneously. However, it is
also safe to power-up the core prior to the I/O block if
simultaneous application of the supplies is not possible. In
this case, the I/O voltage should be applied in 10ms to
100ms nominally to preserve supply component reliability.
Bringing the core and I/O supplies to their respective
regulation levels in a maximum time frame of a 100ms,
moderates the stresses placed on both, the power supply
and the ISL5416.
26
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